1. Field of the Invention
The present invention generally relates to differential amplifier circuits and more particularly to gain enhancement of differential amplifier circuits.
2. Description of Related Art
Persons of ordinary skill in the art understand terms and basic concepts related to microelectronics that are used in this disclosure, such as “differential amplifier,” “positive feedback,” “negative feedback,” “impedance,” “gain,” “DC (direct current) gain,” “transconductance,” “output resistance,” “parasitic capacitance,” and “parasitic resistance.” Terms and basic concepts like these are apparent from prior art documents, e.g. text books such as “Design of Analog CMOS Integrated Circuits” by Behzad Razavi, McGraw-Hill (ISBN 0-07-118839-8), and thus will not be explained or defined herein.
A differential amplifier receives an input signal comprising a first end and a second end and outputs an output signal also comprising a first end and a second end, such that a difference between the first end and the second end of the output signal is greater than a difference between the first end and the second end of the input signal by a gain factor. In many cases, it is desirable for a differential amplifier to have a high gain. In many cases, a high gain, however, is not easy to attain. Zeller et al disclosed a method to enhance a gain of a differential amplifier in “A 0.039 mm2 inverter-based 1.82 mW 68.6 dB-SNDR 10 MHz-BW CT-ΣΔ-ADC in 65 nm CMOS,” IEEE Journal of Solid-State Circuits, VOL. 49, NO. 7, July 2014. However, the method taught by Zeller et al relies on using a cross-coupled latch for gain enhancement, which consumes power and also introduces noise that is approximately equal to a noise contribution from a feed-in network of the differential amplifier, as explained in the aforementioned paper.
What is desired is a method and circuit for enhancing a gain of a differential amplifier without consuming extra power and introducing excess noise.